The present invention relates generally to charge pumps, and more particularly to an improvement which provides substantially reduced output noise compared to prior charge pumps.
On-chip generation of an internal supply voltage at a value greater than the power supply voltage rail VCC has been one approach to providing rail-to-rail operation of an operational amplifier. However, generation of such an internal supply by means of a charge pump circuit has been problematic due to the large amount of output noise (at the charge-pump clock frequency) produced by known charge pumps.
A standard charge pump circuit is a two-phase circuit including two “flying capacitors” and one “reservoir capacitor” which operate to store and maintain the output voltage of the charge pump circuit. FIG. 1A shows a standard charge pump circuit 1, which includes an amplifying circuit 2 having an output 3 connected to a control terminal of a controlled current source 4. Controlled current source 4 produces a current 10. The (−) input of amplifier 2 is connected to VCC. The (+) input of amplifier 2 is connected to the (−) terminal of a voltage source circuit 11, the (+) terminal of which is connected to a conductor 10 which conducts the output signal Vout produced by prior art charge pump 1. The upper terminal of controlled current source 4 is connected to VCC, and its lower terminal is connected to conductor 5. (It should be appreciated that amplifier 2 and controlled current source 4 can be implemented in various ways. For example, amplifier 2 can be implemented by means of a single P-channel transistor having its gate and source connected to the (−) input and (+input), respectively of amplifier 2, and its drain connected to the output 3 of amplifier 2. The implementation of amplifier 2 can be simple or moderately complex, depending on how accurate and/or fast it needs to be. Controlled current source 4 can be implemented by means of a single P-channel transistor having its source connected to VCC, its gate connected to the output 3, and its drain connected to conductor 5. Voltage source circuit 11 can be implemented by means of one or more diode-connected transistors and associated circuitry to achieve a desired voltage drop.)
Charge pump circuit 1 includes a first “flying” capacitor C1 having its upper plate connected by conductor 8 to one terminal of a switch 9 that controllably connects conductor 8 to either VCC or Vout conductor 10. The lower plate of capacitor C1 is connected by conductor 7 to one terminal of a switch 6 that controllably connects conductor 7 to either ground or conductor 5 of controlled current source 4. Charge pump circuit 1 also includes a second flying capacitor C2 having its upper plate connected by conductor 17 to one terminal of a switch 20 that controllably connects conductor 17 to either VCC or Vout conductor 10. The lower plate of capacitor C2 is connected by conductor 16 to one terminal of a switch 15 that controllably connects conductor 16 to either ground or conductor 5 of controlled current source 4. The lower plates of capacitors C1 and C2 are connected by conductors 7 and 16 to parasitic capacitors C1p and C2p, respectively. A relatively large “reservoir” or “output” capacitor Cout is connected between Vout conductor 10 and VCC. A load 13 is connected between Vout conductor 10 and ground.
Each of the two flying capacitors has a recharge phase or “phase 1” (PH1) for charging a flying capacitor to VCC, and also has a subsequent discharge phase or “phase 2” (PH2) for discharging it through Vout conductor 10 into reservoir capacitor Cout or load 13. Discharge through controlled current source 4 is controlled to achieve regulation of Vout.
A drawback of prior art two-phase charge pump circuit 1 is that it has a fast, noise-producing transient process between its above mentioned first and second phases, during which the top plate of one of the flying capacitors is connected to reservoir capacitor Cout at the same time the voltage across the associated parasitic capacitor connected between the bottom plate of that flying capacitor and ground (i.e., the integrated circuit substrate) is still at 0 volts. This causes partial charge redistribution from the reservoir capacitor to the parasitic capacitor thereby producing negative voltage spikes on Vout conductor 10 which constitute a large amount of undesirable noise in the output voltage signal, as illustrated with respect to subsequently described FIG. 2.
Referring to FIG. 1A and the “Switches 6 & 9” and “Switches 15 & 20” waveforms of FIG. 2, switches 6 and 9 are closed during phase 1 of flying capacitor C1 to charge it up to VCC, and alternately, preferably with a 50% duty cycle, switches 15 and 20 are closed to charge C2 up to VCC in such a manner as to effectively maintain Vout at its desired voltage level while supplying whatever current is needed by reservoir capacitor Cout and load 13. The value of the desired regulated voltage level is established by the voltage drop across voltage source circuit 11. Thus, half of the time each flying capacitor is being recharged by being connected between VCC and ground while the other flying capacitor is being controllably discharged into Vout conductor 10 to supply to reservoir capacitor Cout and load 13 whatever amount of current is needed maintain a regulated Vout at its desired voltage. The roles of the two flying capacitors are reversed the other half of the time. A switch control circuit 18 is coupled to control terminals of switches 6, 9, 15 and 20 to control their operation as described herein.
The configurations of switches 6, 9, 15 and 20 are illustrated in FIGS. 1A and 1B for the first half (“Interval 1”) and the second half (“Interval of 2”), respectively, of each cycle of operation of charge pump 1. Specifically, in FIG. 1A, capacitor C1 is in its phase 1 (PH1), with upper switch 9 connected to VCC and switch 6 connected to ground to recharge capacitor C1, and at the same time capacitor C2 is in its phase 2 (PH2), with upper switch 20 connected to Vout and lower switch 15 connected to current source conductor 5 to cause capacitor C2 to be discharged into Vout conductor 10. Similarly, in FIG. 1B capacitor C2 is in its phase 1 (PH1), with upper switch 20 connected to VCC and switch 15 connected to ground to ground to recharge capacitor C2, and at the same time capacitor C1 is in its phase 2 (PH2), with upper switch 9 connected to Vout and lower switch 6 connected to current source conductor 5 to cause capacitor C1 to be discharged into Vout conductor 10.
Thus, as C1 is being recharged while it is connected between VCC and ground, capacitor C2, which has just been charged up to VCC volts, is being discharged into Vout conductor 10 by being connected between the output of controlled current source 4 and Vout conductor 10. At the instant when capacitor C2 is connected between output conductor 10 and conductor 5, the connection to Vout causes the voltage of top plate conductor 17 of capacitor C2 to equal Vout, and the full charge voltage VCC across capacitor C2 causes the voltage of bottom plate conductor 16 to equal Vout−VCC. Then controlled current source 4 begins supplying current 10 through conductor 5 to bottom plate conductor 16, charging up parasitic capacitor C2p and increasing the voltage of bottom plate conductor 16. This also increases the voltage of top plate conductor 17 of capacitor C2 and causes capacitor C2 to discharge through top plate conductor 17 into output conductor 10. Thus, the top plate conductor 17 goes to Vout and the bottom plate conductor 16 goes to Vout−VCC volts. As the current 10 continues to be supplied to bottom plate conductor 16 and increase its voltage, top plate conductor 17 remains at Vout, causing capacitor Cout to discharge a current equal to 10 into output conductor 10. More specifically, amplifier 2 together with controlled current source 4 form a feedback loop which keeps Vout constant (as much as the loop gain allows) and the amount of current 10 is determined by the load current required by load 13 and reservoir capacitor Cout plus some energy loss in the parasitic capacitive dividers.
Amplifier 2 continues to control current source 4 in response to Vout so as to properly regulate Vout, and at the same time, switch control circuit 18 operates according to a suitable 50% duty cycle such that just before the voltage on bottom plate conductor 16 reaches VCC or just before controlled current source 4 saturates, switch control circuit 18 reverses the roles of flying capacitors C1 and C2 so a freshly recharged flying capacitor is available to supply the needed current to output conductor 10. FIG. 1B shows the configuration of switches 9A and 6A and switches 20A and 15A during Interval 2 immediately after the roles of capacitors C1 and C2 have been reversed.
The connection of either one of the flying capacitors, for example capacitor C1, between Vout and conductor 5 causes the above-mentioned noise on Vout conductor 10. At the instant when capacitor C1 is connected between output conductor 10 and controlled current source conductor 5, a capacitive divider circuit is formed which includes parasitic capacitor C1p parasitic and reservoir capacitor Cout. Therefore, some of the charge of reservoir capacitor Cout is redistributed to parasitic capacitance C1p, in accordance with the ratio between them and parasitic capacitance C1p “discharges” or partially discharges reservoir capacitor Cout. This causes a fast negative-going spike in Vout, which constitutes the noise above mentioned noise. Current source 4 then operates to increase Vout from the bottom of that negative-going spike back up to its proper regulated level.
Such negative-going noise spikes occur every time the roles of flying capacitors C1 and C2 are reversed, i.e., the noise occurs at the clock frequency of charge pump 1, as shown in the Vout waveform of FIG. 2. The approximate typical amplitude of the negative noise spikes can be calculated from Vout−Vcc (which can be about 1.5–2.0 volts) and the ratio between reservoir capacitor Cout and the parasitic capacitance C1p or C2p. The reservoir capacitance Cout may be 3 to 5 times the capacitance of the flying capacitors, and the capacitance of a flying capacitor can be roughly 4 to 10 times the associated parasitic capacitance. This can typically result in negative noise spikes of roughly 70 millivolts.
Thus, there is an unmet need for an improved charge pump circuit having substantially reduced output noise.